1. Technical Field
The present invention relates to digital data processors, and more particularly, to interprocessor communication in multiprocessor systems.
2. Background Art
Multiprocessor systems are typically designed such that each processor works independent of the other processors in the system and performs a single task within a given application. When one processor finishes its task on given data, the data is typically passed to another processor to start a next task. In addition, the present state of a given register within one processor may need to be monitored by another processor(s) in order to determine whether or not to perform a next task. Thus, although each processor works as an independent entity in terms of tasks, the processors often rely on data from other processors in the system. System performance is greatly affected by the speed at which these interprocessor data transfers take place. By speeding up interprocessor communication, system performance is correspondingly enhanced.
The principle prior art method of data transfer between processors involves an external write by one processor with a corresponding read by another. In the simplest form, one processor writes to an external memory location, and another processor subsequently reads that location to obtain the data. While accomplishing the goal of interprocessor data transfer, this method hinders system performance in a number of ways. For example, for every data transfer it takes at least two cycles; one for the write and one for the read. Also, the bus or buses used for the data transfers to and from data memory may not be available when a processor seeks to write to or read from memory, thus causing a further delay in the transfer.
An example of this prior art method can be found in U.S. Pat. No. 4,754,398, entitled "System for Multiprocessor Communication Using Local and Common Semaphore and Information Registers," and issued to Richard D. Pribnow. The Pribnow patent discloses what is basically a system involving the sharing of external common registers, rather than external data memory, wherein data is written and subsequently read from. Although processors can directly access these shared registers, the data must still be placed in the registers and then removed.